Field of the Invention
The invention relates to an electronic system diagnostic technology, and more specifically relates to an electronic system, a system diagnostic circuit, and an operation method.
Description of Related Art
More and more transistors are integrated in a single chip as the complexity of a circuit design growing, it increases the execution time of a scan test for a chip. For example, FIG. 1 is a circuit block diagram depicting a system with Joint Test Action Group (JTAG) standard (or IEEE 1149.1 standard). An electronic system 100 represents a target system that is diagnosed. Diagnostic operations include (but not limit to) debug, performance monitoring, tracing, testing and firmware programming.
The electronic system 100 can include a memory 110 and/or other system devices 120. The electronic system 100 can also include a plurality of processors (such as the processors 130, 140, and 150 shown in FIG. 1). Each of the processors 130, 140, and 150 can access/control the memory 110 and/or the system devices 120 via the system bus 160. Each of the processors 130, 140, and 150 includes a core circuit and a test access port (TAP), as shown in FIG. 1.
The test data output terminal TDO of a diagnosis host 10 is coupled to the test data input terminal TDI of the test access port of the processor 130, the test data output terminal TDO of the test access port of the processor 130 is coupled to the test data input terminal TDI of the test access port of the processor 140, the test data output terminal TDO of the test access port of the processor 140 is coupled to the test data input terminal TDI of the test access port of the processor 150, and the test data output terminal TDO of the test access port of the processor 150 is coupled to the test data input terminal TDI of the diagnosis host 10. Therefore, the coupling relationship between the processors 130, 140, 150 and the diagnosis host 10 is represented as a daisy-chain structure. The processors 130, 140, and 150 form a scan chain.
The diagnosis host 10 outputs a test clock signal TCK, a test mode selection signal TMS, and a reset signal TRST to the test access ports of the processors 130, 140, 150. According to the activation of the test mode selection signal TMS, the test access ports of the processors 130, 140, and 150 can switch operating state. Therefore, the test access ports of the processors 130, 140, and 150 can execute a test instruction that is issued from the diagnosis host 10, and can return a test result to the diagnosis host 10. However, during operation of the system and considering the power management, power supply of one or a plurality of the processors 130, 140, and 150 can be turned off. When power supply of any of the test access ports in the scan chain is turned off, the scan chain is disconnected so that the diagnosis host 10 cannot monitor and/or test the electronic system 100.